1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and more specifically, to a method for using a PLL in a recordable optical disk drive to perform phase shift detection while recording to a recordable disk.
2. Description of the Prior Art
A phase locked loop is used for frequency control. Please refer to FIG. 1. FIG. 9 is a block diagram of a phase locked loop (PLL) 10 for controlling a recordable optical disk drive according to the prior art. The PLL 10 generates a clock signal CLK in response to a wobble signal WOBBLE. The wobble signal WOBBLE is extracted from the wobble tracks of a recordable optical disk, as shown in FIG. 2, and contains address information of the wobble tracks. The clock signal CLK is used to control the writing path of the recordable drive and is the reference for the recording clock. A period of the wobble signal WOBBLE corresponds to 186 periods of the clock signal CLK for a DVD-R/RW specification, and a period of the wobble signal WOBBLE corresponds to 32 periods of the clock signal CLK in a DVD+R/RW specification. To ensure synchronized writing data to the correct track at the right time, the PLL synchronizes the clock signal CLK with the wobble signal WOBBLE.
The PLL 10 contains a phase detector 12, which is used for comparing phases of the wobble signal WOBBLE and the clock signal CLK. Based on a phase difference between the wobble signal WOBBLE and the clock signal CLK, the phase detector 12 then outputs either an up signal UP or a down signal DN to a charge pump circuit 14. Based on receipt of either the up signal UP or the down signal DN, the charge pump circuit 14 sends or receives a control current to a loop filter 16. Next, a control voltage is outputted from the loop filter 16 and fed into a voltage controlled oscillator (VCO) 18. The VCO 18 generates the clock signal CLK with an output frequency based on the control voltage. An optional frequency divider 20 can be used for dividing the frequency of the clock signal CLK, and finally the clock signal CLK is fed back into the phase detector 12. Together, the phase detector 12, the charge pump circuit 14, the loop filter 16, the VCO 18, and the frequency divider 20 form the PLL 10, which is a feedback loop.
However, sometimes the PLL 10 cannot synchronize the phase of the clock signal CLK with the phase of the wobble signal WOBBLE due to a phase shift phenomenon. The phase shift phenomenon occurs due to a limit of the conventional phase detector 12. Please refer to FIG. 3A through FIG. 3E. FIG. 3A through FIG. 3E are phase shift diagrams illustrating operation of the phase detector 12 under various circumstances. Based on an input phase shift xcex8e, the phase detector 12 generates an output ud for correcting the phase shift xcex8e. The output u d is shown in FIG.1 as either being the up signal UP or the down signal DN, and is used to synchronize the clock signal CLK with the wobble signal WOBBLE. As long as the phase shift xcex8e is within a locking range a xcex94wL of the phase detector 12, the phase detector 12 is able to synchronize the clock signal CLK with the wobble signal WOBBLE. The locking range xcex94wL of the phase detector 12 is usually equal to a phase difference of plus or minus half a period of the wobble signal WOBBLE. As will be shown shortly, a problem occurs when the phase shift xcex8e falls outside of the locking range xcex94wL of the phase detector 12.
In FIG. 3A, point 30 represents the output function of the phase detector 12. Because the phase shift xcex8e has a value of 0, no action is needed by the phase 12 to correct the phase shift xcex8e, and the phase detector 12 outputs a corresponding output ud also having a value of 0. When the phase shift xcex8e does not have a value of 0, the output function of the phase detector moves along the diagonal lines shown in FIG. 3A. When the phase shift xcex8e becomes larger than the locking range xcex94wL, the output function will follow the diagonal lines shown outside of the locking range xcex94wL. Point 30 is located at a crossing point, which is where the diagonal lines of the output function pass through the axis representing the phase shift xcex8e, and each crossing point has an output ud of 0.
The job of the phase detector 12 is to correct the phase shift xcex8e such that the phase shift xcex8e always locks onto the point 30 shown in FIG. 3A since this is the only way the phase shift xcex8e will have a value of 0. As long as the phase shift xcex8e is within the locking range xcex94wL, the phase detector 12 will track and lock the phase shift xcex8e to have a value of 0. Notice that just because the output ud d has a value of 0, it does not necessarily imply that the phase shift xcex8e has a value of 0.
In FIG. 3B, point 32 shows a case in which the inputted phase shift xcex8e has a value greater than 0, but is still within the locking range xcex94wL. Since point 32 is not located on a crossing point, the phase detector 12 will generate the output ud in order to lock the phase shift xcex8e onto the nearest crossing point. FIG. 3C shows the result of this, and point 34 shows the locking of the phase shift xcex8e onto the crossing point in the middle of the locking range xcex94wL. Since point 32 in FIG. 3B was within the locking range xcex94wL, point 34 in FIG. 3C is locked to the crossing point in the locking range xcex94wL, and not locked to one of the crossing points outside of the locking range xcex94wL.
FIG. 3D and FIG. 3E show the problems that arise when the phase shift xcex8e is not in the locking range xcex94wL. In FIG. 3D, point 36 shows a case in which the inputted phase shift xcex8e has a value greater than 0, and is not within the locking range xcex94wL. Since point 36 is not located on a crossing point, the phase detector 12 will generate the output ud in order to lock the phase shift xcex8e onto the nearest crossing point. FIG. 3E shows the result of this, and point 38 shows the locking of the phase shift xcex8e onto the crossing point that is immediately to the right of the locking range xcex94wL. Since point 36 in FIG. 3D was to the right of the locking range xcex94wL, point 38 in FIG. 3E is locked to the crossing point to the right of the locking range xcex94wL, and not the crossing points in the middle of the locking range xcex94wL.
Please refer to FIG. 4A through FIG. 4E. FIG. 4A through FIG. 4E are circular phase shift diagrams analogous to FIG. 3A through FIG. 3E, respectively. The circular phase diagrams of FIG. 4A through FIG. 4E are another way of representing the information in the phase diagrams of FIG. 3A through FIG. 3E, and are shown for convenience. In FIG. 4A to FIG. 4E, the dotted circles are used to represent a continuous, loop characteristic of the phase shift xcex8e. The horizontal line running through the dotted circle represents the locking range xcex94wL. The right side of the horizontal line is labeled xe2x80x9c0xe2x80x9d, and represents a phase shift xcex8e of 0+n * xcex94wL, where n is an integer such as 1, 2, 3, etc. The left side of the horizontal line is labeled xe2x80x9cxc2x1xc2xd xcex94wLxe2x80x9d, and represents, a phase shift xcex8e of xc2xd xcex94wLxc2x1m * xcex94wL, where m is also an integer such as 1, 2, 3, etc.
In FIG. 4A, point 40 represents the output function of the phase detector 12. Because the phase shift xcex8e has a value of 0, no action is needed by the phase 12 to correct the phase shift xcex8e , and the phase detector 12 outputs a corresponding output ud also having a value of 0. Please notice that just because the output ud has a value of 0, it does not necessarily imply that the phase shift xcex8e has a value of 0. The phase shift xcex8e could also have a value of 0+n * xcex94wL.
In FIG. 4B, point 42 shows a case in which the inputted phase shift xcex8e has a value greater than 0, but is still less than xc2xd xcex94wL. Since at point 42 the phase shift xcex8e does not have a value of 0+n * xcex94wL the phase detector 12 will generate the output ud in order to lock the phase shift xcex8e onto the nearest crossing point with a phase shift xcex8e value of 0+n * xcex94wL Note that in FIG. 4B, both the phase shift xcex8e and the output ud have a positive value.
FIG. 4C illustrates the result of the phase detector 12 correcting the phase shift xcex8e present in FIG. 4B. Point 44 shows the locking of the phase shift xcex8e onto the crossing point in the middle of the locking range xcex94wL Since point 42 in FIG. 4B has a phase shift xcex8e less than xc2xd xcex94wL point 44 in FIG. 4C is locked to the crossing point in the locking range xcex94wL and not one of the crossing points outside of the locking range xcex94wL Therefore, as long as the phase shift xcex8e is less than xc2x1xc2xd xcex94wL, the phase detector 12 can reduce the phase shift xcex8e to a value of 0.
FIG. 4D and FIG. 4E show the problems that arise when the phase shift xcex8e is not less than xc2x1xc2xd xcex94wL In FIG. 4D, point 46 shows a case in which the inputted phase shift xcex8e has a value greater than xc2xd xcex94wL, and is not within the locking range xcex94wL. Since point 46 is not located on a crossing point, the phase detector 12 will generate the output ud in order to lock the phase shift xcex8e onto the nearest crossing point. Note that in FIG. 4D the phase shift xcex8e has a positive value, but the output ud has a negative value.
FIG. 4E shows result of the phase detector 12 correcting the phase shift xcex8e present in FIG. 4D. Point 48 shows the locking of the phase shift xcex8e onto the crossing point that was closest to the phase shift xcex8e . Since point 46 in FIG. 4D was greater than xc2xd xcex94wL, point 48 in FIG. 4E is locked to the crossing point in which the output ud has a value of 0 and the phase shift xcex8e has a value of xcex94wL. Once the output function of the phase detector 12 is locked to point 48, it is very difficult for the phase detector 12 to correctly eliminate the phase shift xcex8e.
One of the problems with not eliminating the phase shift xcex8e between the wobble signal WOBBLE and the clock signal CLK is the clock signal CLK will have the incorrect period required for correctly recording data onto an optical disk. If the period of the clock signal CLK is too long, the density of data stored on the optical disk will be to small. On the other hand, if the period of the clock signal CLK is too short, the density of data stored on the optical disk will be too high. For an illustration of this problem, please refer to FIG. 5. FIG. 5 is diagram showing the effects of recording data onto an optical disk while using a clock signal CLK with an incorrect period. FIG. 5 illustrates three cases. The first case is an ideal case in which the clock signal CLK is in phase with the wobble signal WOBBLE and properly records data onto the optical disk. As shown in FIG. 5, the optical disk is shown as having three blocks labeled as block 1 of disk, block 2 of disk, and block 3 of disk. In the ideal case, each data block to be written onto the optical disk (such as DATA block 1) is written such that the data block exactly fits into each corresponding block of the optical disk. Therefore, there are no data blocks that are partially written into more than one block of the optical disk.
In the second and third cases, the frequency of the clock signal CLK is not in phase with the wobble signal WOBBLE, and has a period that is too long. When the period of the clock signal CLK is too long, there are two main schemes for dealing with the situation. The first is to connect the beginning of new data blocks to the end of previously written data blocks. However, the problem with this scheme is the location of all subsequent data blocks will be shifted, and will not properly fit into each block of the optical disk. The second scheme is to ignore the ending location of the previous data block and to align the beginning location of new data blocks with the position of the block on the disk. Unfortunately, the problem with this scheme is data will overlap and the data in the new data block will overwrite part of the data contained in the previous data block.
Other prior art devices and methods% have been used to help correct the problem of misaligning data blocks onto blocks of optical disks. In U.S. Pat. No. 6,269,059 entitled xe2x80x9cApparatus for and method of adding information onto recording medium that enables additional recordingxe2x80x9d, Kuroda et al. disclose a prior art apparatus and method for recording information on a recording medium, which is included herein by reference Kuroda et al. teach a recordable optical disk drive that uses pre-pits stored in an optical disk to synchronize and align data blocks to be written to the disk with corresponding blocks on the disk. The pre-pits on the optical disk contain physical address information about the corresponding blocks of the optical disk. By decoding the address information stored in the pre-pits, the recordable optical disk drive can record new data blocks onto the optical disk such that each new data block is written at the beginning of each corresponding block on the disk. By using the pre-pits to synchronize data with the corresponding blocks on the disk, the recordable optical disk drive can overcome any phase shift xcex8e that exists between the wobble signal WOBBLE and the clock signal CLK.
However, to take advantage of the physical address information stored in the pre-pits of the optical disk, the recordable optical disk drive requires a physical address decoder to decode the physical address information. The use of the physical address decoder means that extra hardware is required for the recordable optical disk drive, and thereby increases the price and complexity of the recordable optical disk drive. Another problem with the prior art method proposed by Kuroda et al. is the need to wait for each pre-pit in order to synchronize. After the physical address information is decoded from a pre-pit, there is no way to synchronize data blocks written to the optical disk until the next pre-pit is decoded. Moreover, address decoding is not always completely reliable, and address decoding requires sophisticated address prediction in order to compensate for problems that arise when decoding physical addresses.
It is therefore a primary objective of the claimed invention to provide a method of generating an output signal from a phase locked loop (PLL) such that the output signal maintains a substantially constant phase difference with respect to a phase of a reference signal in order to solve the above-mentioned problems.
According to the claimed invention, a method of generating an output signal from a phase locked loop (PLL) such that the output signal maintains a substantially constant phase difference with respect to a phase of a reference signal is introduced. The PLL comprises a phase detector for comparing phases of the output signal and the reference signal with each other and producing a corresponding comparison signal, a charge pump for receiving the comparison signal from the phase detector and producing a control current based on the comparison signal, a loop filter for receiving the control current from the charge pump and producing a corresponding control voltage, and a voltage controlled oscillator (VCO) for receiving the control voltage from the loop filter and producing an oscillation signal based on the control voltage. The PLL further comprises a first frequency divider for dividing a frequency of the oscillation signal by a first divisor, and for generating a number of multiphase signals, such that each multiphase signal is out of phase with each of the other multiphase signals, a phase adjusting circuit for selecting one of the multiphase signals generated by the first frequency divider to be the output signal, and a phase shift detection circuit for comparing a phase of the oscillation signal with the phase of the reference signal. The present invention method comprises steps: the phase shift detection circuit sampling the phase difference between the oscillation signal and the reference signal a predetermined number of times during each period of the reference signal and storing each of the phase differences in a memory in order to calculate a total phase difference between the oscillation signal and the reference signal at the end of each period of the reference signal; the phase shift detection circuit generating an adjustment control signal in response to the total phase difference between the oscillation signal and the reference signal; and the phase adjusting circuit selecting one of the multiphase signals to be the output signal according to instructions in the adjustment control signal, and outputting the output signal to the phase detector, wherein the output signal is selected such that a phase difference between the output signal and the reference signal is greater than the total phase difference between the oscillation signal and the reference signal for causing the phase detector to reduce the phase difference between the oscillation signal and the reference signal.
It is an advantage of the claimed invention that the method can synchronize the reference signal with the output signal, even if the phase difference between the oscillation signal and the reference signal exceeds half of the period of the reference signal, which is the limit of a conventional phase detector. The clock signal can therefore stay in phase with the wobble signal, and data blocks can be correctly written to corresponding blocks on an optical disk. It is also an advantage that the phase difference between the wobble signal and the clock signal can be calculated in real time, eliminating the need to wait for a pre-pit for synchronization which was the case in the prior art.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.